Editorial

Parsa Wireless Communications is pleased to publish bimonthly technical briefs focusing on different technologies in every issue.  This issue is dedicated to semiconductor technologies.  We have a short brief on advances and future of CMOS technology and also current state and future of memory technologies. We are also featuring a Reverse Engineering work done by our expert on a memory chip using publicly available data. The future 10 issues will be on: Telecom, SDN, Consumer Electronics, Audio and Video, Routers and Internet, Automotive, Mobile Technologies, Medical Devices and Mobile Core Networks. We welcome your feedback as these different technical briefs come out. Please note that these briefs are  quite short and are comprised of a few slides. 

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Reverse Engineering Project: Memory Chip

The challenges included identifying structures and materials through a series of primarily destructive processes, ensuring that data is gathered before sections are removed and that the processes do not change the structure of the memory chip. Additionally, we were tasked with understanding the manufacturing process, which often includes intermediate materials not present in the final product, as well as changes to shape or material compositions due to heat, pressure, or other manufacturing processes.

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Current state and future of Memory

SRAM

  • High performance symmetric Array read/write (sub 10ns)
  • Used as Cache for CPU,  Packet processing, High random transaction rates.
  • Synchronous & pipeline architectures enhance performance.
  • Manufactured in logic process on same die as CPU.
  • 6T (Transistor) bit cell , highest die cost, limits density
  • Static data storage (no refresh of data required unlike DRAM)=> Lower power than DRAM
  • Loss of data when power is removed (non-persistent)
  • Cache algorithm needed to ensure coherency (i.e. latest version of data resides in accessed location)
  • Reliability issue: Soft errors
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Current state and future of CMOS Process technology area

  • —While Moore scaling is continuing, the trend is slowing down
  • —TSMC is not scaling its 16nm process from the 20nm process – same transistor size
  • —GF and Samsung following suit
  • —Wafer cost is increasing faster than transistor scaling
  • —This is due to ever increasing process complexity
  • —Lithography is still based on UV stepper technology
  • —Quad patterning will likely be needed on the next node before EUV is available
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In This Issue

Editorial

Special Services: Expert-Based Prior Art Search Subscription

Reverse Engineering Project: Memory Chip


Current state and future of Memory

Current state and future of CMOS Process technology area

 
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Reverse Engineering Project: Memory Chip



Current State and Future of Memory


Current State and Future of CMOS Process Technology Area
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